Chapter 2: Digital Abstraction
Chapter 3: CMOS Technology
Chapter 4: Gates
Chapter 5: Logic Synthesis
Chapter 6: Sequential Logic
Chapter 7: (Synchronous) Finite State Machines
Chapter 8: Synchronization, Metastability and Arbitration
Chapter 9: Pipelining
Chapter 10: Cost/Performance Tradeoffs
Chapter 11: Programmability
Chapter 12: Designing an Instruction Set
Chapter 13: Machine Language, Assemblers,and Compilers
Chapter 14: Stacks and Procedures
Chapter 15: Building the Beta
Chapter 16: Pipelining the Beta
Chapter 17: Pipeline Issues
Chapter 18: The Memory Hierarchy
Chapter 19: Cache Issues
Chapter 20: Interconnect and Communication
This material was created by or adapted from material created by MIT faculty member, Steve Ward, Chris Terman, Professors, 2002. Copyright © 2002 Steve Ward, Chris Terman.
This material is licensed by the Massachusetts Institute of Technology under a Creative Commons License.
This license is available at: http://ocw.mit.edu/OcwWeb/Global/terms-of-use.htm
This material is licensed by the Massachusetts Institute of Technology under a Creative Commons License.
This license is available at: http://ocw.mit.edu/OcwWeb/Global/terms-of-use.htm